This disclosure relates to a recessed semiconductor device and, more particularly, to a refresh characteristic test circuit capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic.
Recently, as the semiconductor memory device is highly integrated and the design rule is dramatically decreased, it is more difficult to guarantee a stable operation of transistors in the memory device. For example, with the decrease of a gate in the transistor, a channel length is more decreased and the short channel effect is then caused frequently. Due to the short channel effect, the punch-through is seriously caused between a source and a drain in the highly integrated semiconductor memory device and this punch-through is mainly responsible for the malfunction of the transistor. Accordingly, various methods to guarantee the long channel without the increase of the design rule has been developed in order to overcome the short channel effect. Particularly, a recessed gate structure, which is capable of enlarging the channel length within the limited gate width, comes into the spotlight of highly integrated semiconductor memory devices, manufactured by recessing a semiconductor substrate and enlarging the channel length.
The increase of the channel length makes an amount of ions, which are implanted into the semiconductor substrate for the threshold voltage, reduced. Accordingly, the semiconductor device having the recessed gate structure can increase the refresh time, as compared to the planar gate structure. Charges stored in a capacitor of a storage node are lost due to the generation/recombination current (i.e., leakage current) which are generated by traps in a depletion region of a storage node. The refresh time can be taken by a time interval which is required to retain the information stored in a capacitor and then to sense the information in a sense amplifier.
FIG. 1 is a layout showing a cell array of a semiconductor device having a recessed gate structure. The semiconductor memory device shown in FIG. 1 having the recessed gate structure includes neighbor gates N8 to N10 and passing gates N3, N4, N11 and N12 which are inevitably required to form a cell array. The neighbor gates N8 to N10 are formed in the same region as selected gates N5 to N7 to which voltage is applied when a second word line WL2 is selected. The formation region of the passing gates N3, N4, N11 and N12 are different from that of the selected gates N5 to N7. Even if voltage is not directly applied to a first word line WL1, a third word line WL3 and a fourth word line WL4, the neighbor gates N8 to N10 and the passing gates N3, N4, N11 and N12, which are in a turn-off state, are changed into the sub-threshold state by the voltage applied to the second word line WL2 and then increase the leakage current. This leakage current increase of the neighbor gates N8 to N10 and the passing gates N3, N4, N11 and N12 is called “neighbor/passing gate effect” in the turn-off state.
However, when the neighbor/passing gate effect is caused, the leakage current which is generated by the traps is rapidly increased by the trap-assisted tunneling effect. This increase of the leakage current decreases the refresh time and causes refresh failure.